This invention relates to a semiconductor integrated circuit. Particularly, it relates to a structure of the interconnection portion in the semiconductor integrated circuit.
FIG. 1 shows an example of the structure of a conventional semiconductor integrated circuit. In the Figure, two insulated-gate field effect transistors (MOSTs) 8 and 9 are illustratively shown as elements within the integrated circuit. Referring to FIG. 1, numeral 2 designates a semiconductor (e.g. Si) substrate of the p-type conductivity, numerals 3, 301, 302, 303, and 304 insulating films (of, e.g. SiO.sub.2), numerals 501, 502, 503, and 504 source and drain regions (n.sup.+ -type regions), numerals 101, 103, 104, and 106 source and drain electrodes, and numerals 102 and 105 gate electrodes. Shown at numeral 1 is an interconnection layer within the integrated circuit, which is disposed on the thick insulating film 3 for isolating the elements from each other and which connects the electrodes 101-106 of the elements appropriately. In the structure of FIG. 1, the two MOSTs 8 and 9 are isolated from each other by the thick insulating film 3 and a p.sup.+ -type region (not shown) underlying it.
In the semiconductor integrated circuit (IC), especially a largescale integrated circuit (LSI), as shown in FIG. 1, the parasitic capacitance of the interconnection increases with the increase of the packing density. For high speed operation of the integrated circuit, however, the parasitic capacitance of the interconnection needs to be reduced. In an LSI employing a silicon (Si) body (substrate, eptiaxialgrown layer, well-diffused layer, or the like), a thick insulating film (of, e.g. SiO.sub.2) 3 for isolating the elements has heretofore been provided between the interconnection layer 1 and the silicon body 2 as shown in FIG. 1. In this case, the capacitance C between the interconnection layer 1 and the silicon body 2 is expressed as a series capacitance which consists of a capacitance C.sub.ox due to the SiO.sub.2 film 3 and a capacitance C.sub.d due to a depletion layer 4 underneath this SiO.sub.2 film. Since, however, a channel stopper layer of high impurity concentration is usually formed in the surface of the silicon body underlying the SiO.sub.2 film 3, the depletion layer 4 (dotted line) does not extend sufficiently thick underneath the SiO.sub.2 film 3. Therefore, the capacitance C between the interconnection layer 1 and the silicon body 2 is substantially determined by the capacitance C.sub.ox due to the SiO.sub.2 film 3 underneath the interconnection layer. In order to reduce this capacitance C.sub.ox, the thickness of the SiO.sub.2 film 3 needs to be increased. However, when the thickness of the insulating film 3 is increased, the height of the step or raised portion of the surface of the integrated circuit becomes large, leading to such problems as severance of the interconnection layer, etc. A reduction of the interconnection parasitic capacitance by increasing the thickness of the insulating film is, therefore, subject to limitations.
Accordingly, the semiconductor integrated circuit has had the problem that even when the packing density is enchanced, the parasitic capacitance of the interconnection is increased thereby hampering the high speed operation of the circuit.